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CY8CTMG120 truetouch? multi-touch gesture touchscreen controller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-46929 rev. *b revised july 29, 2008 features truetouch ? capacitive touchscreen controller ? supports single-touc h and multi-touch touchscreen control ? supports up to 44 x/y sensor inputs ? supports screen sizes 8.4? and below ? fast scan rates: typical 0.5 ms per sensor ? high resolution: typical 480 x 360 for 3.5? screen ? available in 56-pin qfn package ? seamless transition up to higher function multi-touch all-point device lowest noise truetouch device highly configurable sensing circuitry ? allows maximum design flexibility ? allows trade-off between scan time and noise perfor- mance includes gesture detection library develop customized us er defined gestures provides maximum emi immunity ? selectable spread-spectrum clock source powerful harvard architecture processor ? m8c processor speeds to 24 mhz ? two 8x8 multiply, 32-bit accumulate ? low power at high speed ? 3v to 5.25v operating voltage ? industrial temperature range: ?40c to +85c ? usb temperature range: ?10c to +85c full-speed usb (12 mbps) ? four uni-directional endpoints ? one bi-directional control endpoint ? usb 2.0 compliant ? dedicated 256 byte buffer ? no external crystal required flexible on-chip memory ? 16k flash program storage, 50000 erase/write cycles ? 1k sram data storage ? in-system serial programming (issp) ? partial flash updates ? flexible protection modes ? eeprom emulation in flash precision, programmable clocking ? internal 4% 24 and 48 mhz oscillator ? internal oscillator for watchdog and sleep ? 0.25% accuracy for usb with no external components additional system resources ? i 2 c ? slave, master, and multi-master to 400 khz ? watchdog and sleep timers ? user-configurable low voltage detection ? integrated supervisory circuit ? on-chip precision voltage reference complete development tools ? free development software (psoc designer?) ? truetouch touchscreen tuner ? full-featured, in-circuit emulator and programmer ? full speed emulation ? complex breakpoint structure ? 128k bytes trace memory programmable pin configurations ? 25 ma sink, 10 ma drive on all gpio ? pull up, pull down, high z, strong, or open drain drive modes on all gpio ? configurable interrupt on all gpio logic block diagram [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 2 of 33 truetouch functional overview the truetouch family provides the fastest and most efficient way to develop and tune a capacitive touchscreen application. a truetouch device includes the configurable truetouch block, configurable analog and digital logic, programmable inter- connect, and an 8-bit cpu to run custom firmware. this archi- tecture enables the user to cr eate flexible, customized touch- screen configurations to ma tch the requirements of each individual touchscreen application. various configurations of flash program memory, sram data memory, and configurable io are included in a range of convenient pinouts. the truetouch architecture is comprised of four main areas: the core, digital system, the truetouch analog system, and system resources including a full-speed usb port. configurable global busing allows all the device resources to be combined into a complete custom touchscreen system. the CY8CTMG120 device can have up to seven io ports that connect to the global digital and analog interconnects, providing access to four digital blocks and six analog blocks. implementation of touchscreen application allows additional digital and analog resources to be used, depending on the touchscreen design. the CY8CTMG120 is offered in a 56-pin qfn package, with up to 48 general purpose io (gpio), and support of up to 44 x/y sensors. when designing touchscreen applications, refer to the um data sheet for performance requirements to meet and detailed design process explanation. the truetouch core the core includes a cpu, memory, clocks, and configurable gpio (general purpose io). the m8c cpu core is a powerful processor with speeds up to 24 mhz, providing a four mips 8-bit harvard architecture micropro- cessor. the cpu uses an interrupt controller with up to 20 vectors, to simplify programming of real time embedded events. program execution is timed an d protected using the included sleep and watch dog timers (wdt). memory encompasses 16k of flash for program storage, 1k of sram for data storage, and up to 2k of eeprom emulated using the flash. program flash uses four protection levels on blocks of 64 bytes, allowing cust omized software ip protection. the truetouch device incorporates flexible internal clock gener- ators, including a 24 mhz imo (int ernal main oscillator) accurate to 8% over temperature and voltage. the 24 mhz imo can also be doubled to 48 mhz for use by the digital system. a low power 32 khz ilo (internal low speed oscillator) is provided for the sleep timer and wdt. the clocks, together with programmable clock dividers (as a system resou rce), provide the flexibility to integrate almost any timing requi rement into the psoc device. in usb systems, the imo self-tunes to 0.25% accuracy for usb communication. the gpios provide connection to the cpu, digital and analog resources of the device. each pin?s drive mode may be selected from eight options, allowing great flexibility in external inter- facing. every pin also has the capability to generate a system interrupt on high level, low le vel, and change from last read. the digital system the digital system is composed of 4 digital psoc blocks. each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16 , 24, and 32-bit peripherals, which are called user module references. figure 1. digital system block diagram digital peripheral configurations include those listed below. full-speed usb (12 mbps) pwms (8 to 32 bit) pwms with dead band (8 to 24 bit) counters (8 to 32 bit) timers (8 to 32 bit) uart 8 bit with selectable parity spi master and slave i2c slave and multi-master pseudo random sequence generators (8 to 32 bit) the digital blocks are connected to any gpio through a series of global buses that can route any signal to any pin. the buses also allow signal multiplexing and performing logic operations. this configurability frees your de signs from the constraints of a fixed peripheral controller. digital blocks are provided in rows of four, where the number of blocks varies by truetouch device family. this allows optimum choice of system resources for your application. family charac- teristics are shown in table 1 on page 4. digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital psoc block array to analog system 8 row input configuration row output configuration 8 8 8 row 0 dbb00 dbb01 dcb02 dcb03 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect port 1 port 0 port 3 port 2 port 5 port 4 port 7 [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 3 of 33 the analog system the analog system is composed of 6 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. analog peripherals are very flexible and can be customized to support spec ific application requirements. some of the more common psoc analog functions (most available as user modules) are listed below. analog-to-digital converters (up to 2, with 6- to 14-bit resolution, selectable as incremental, delta sigma, and sar) filters (2 and 4 pole band-pass, low pass, and notch) amplifiers (up to 2, with selectable gain to 48x) instrumentation amplifiers (1 with selectable gain to 93x) comparators (up to 2, with 16 selectable thresholds) dacs (up to 2, with 6- to 9-bit resolution) multiplying dacs (up to 2, with 6- to 9-bit resolution) high current output drivers (two with 30 ma drive as a psoc core resource) 1.3v reference (as a system resource) modulators correlators peak detectors many other topologies possible analog blocks are arranged in a co lumn of three, which includes one ct (continuous time) and two sc (switched capacitor) blocks, as shown figure 2 . the analog multiplexer system the analog mux bus connects to every gpio pin in ports 0-5. pins are connected to the bus individually or in any combination. the bus also connects to the analog system for capacitive sensing with the truetouch block comparator. it can be split into two sections for simultaneous dual-channel processing. an additional 8:1 analog input multipl exer provides a second path to bring port 0 pins to the analog array. switch control logic enables selected pins to switch dynamically under hardware control. this allo ws capacitive measurement for the touchscreen applications. other multiplexer applications include: chip-wide mux that allows analog input from up to 48 io pins. electrical connection between any io pin combinations. figure 2. analog system block diagram additional system resources system resources, provide additional capability useful to complete systems. additional resources include a multiplier, decimator, low voltage detection, and power on reset. brief state- ments describing the merits of each resource follow. full-speed usb (12 mbps) with 5 configurable endpoints and 256 bytes of ram. no external components required except two series resistors. wider th an commercial temperature usb operation (-10c to +85c). digital clock dividers provide three customizable clock frequencies for use in applications. the clocks can be routed to both the digital and analog systems. additional clocks can be generated using digital psoc blocks as clock dividers. two multiply accumulates (macs) provide fast 8-bit multipliers with 32-bit accumulate, to assist in both general math and digital filters. acb00 acb01 block array array input configuration ac i1[1:0] asd20 ac i0[1:0] p0[6] p0[4] p0[2] p0[0] p2[2] p2[0] p2[6] p2[4] refin agndin p0[7] p0[5] p0[3] p0[1] p2[3] p2[1] reference generators agndin refin bandgap refhi reflo agnd asd11 asc21 asc10 interface to digital system m 8c interface (address bus, data bus, etc.) analog reference all io (except port 7) analog mux bus [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 4 of 33 decimator provides a custom har dware filter for digital signal processing applications including creation of delta sigma adcs. the i2c module provides 100 and 400 khz communication over two wires. slave, master, multi-master are supported. low voltage detection (lvd) interrupts signal the application of falling voltage levels, while the advanced por (power on reset) circuit eliminates t he need for a system supervisor. an internal 1.3v reference provides an absolute reference for the analog system, includ ing adcs and dacs. versatile analog multiplexer system. getting started to understand the psoc silicon, read this data sheet and use the psoc designer integrated de velopment environment (ide). this data sheet is an overview of the psoc integrated circuit and presents general silicon and electrical specifications. for in depth touchscreen application information, including touch- screen specific specifications, read the touchscreen user module data sheet that is supported by this specific device. truetouch device characteristics depending on the truetouch device selected for a touchscreen application, characteristics and capabilities of each device change. ta b l e 1 lists the touchscreen sensing capabilities available for specific truetouch devices. the truetouch device covered by this data sheet is highlighted in this table. development kits development kits are available from the following distributors: digi-key, avnet, arrow, and future. the cypress online store contains development kits, c compilers, and all accessories for psoc development. go to the cypress online store web site at http://www.cypress.com, click the online store shopping cart icon at the bottom of the web page, and click psoc (program- mable system-on-chip) to view a current list of available items. technical training modules free psoc technical training modules are available for users new to psoc. training modules cover designing, debugging, advanced analog and capsense. go to http://www.cypress.com/training . consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to http://www.cypress.com, click on design support located on the left side of the web page, and select cypros consultants. technical support psoc application engineers take pride in fast and accurate response. they are available with a four hour guaranteed response at http://www.cypress.c om/support/login.cfm . application notes a long list of application notes assi st you in every aspect of your design effort. to view the psoc application notes, go to the http://www.cypress.com web site and select application notes under the design resources list located in the center of the web page. application notes are li sted by date as default. development tools psoc designer is a microsoft ? windows based, integrated development environment for the programmable system-on-chip (psoc) devices. the psoc designer ide and application runs on windows nt 4.0, windows 2000, windows millennium (me), or windows xp (see figure 3 on page 5). psoc designer helps the customer to select an operating config- uration for the psoc, write applic ation code that uses the psoc, and debug the application. this system provides design database management by project, an integrated debugger with in-circuit emulator (ice), in-system programming support, and the cyasm macro assembler for the cpus. psoc designer also supports a high level c language compiler developed specifically for the devices in the family. table 1. truetouch device characteristics truetouch part number sensor inputs max screen size (inches) single-touch multi-touch gesture multi-touch all-point scan speed (ms) [1] current consumption [2] flash size sram size cy8ctst110 up to 24 4.3? y n n 0.5 3 8k 512 bytes cy8ctst120 up to 44 8.4? y n n 0.5 16 16k 1k cy8ctmg110 up to 24 4.3? y y n 0.5 3 8k 512 bytes CY8CTMG120 up to 44 8.4 y y n 0.5 16 16k 1k cy8ctma120 up to 37 7.3? y y y 0.12 16 16k 1k notes 1. per sensor typical. depends on touchscreen panel. for ma120 per x/y crossing vcc = 3.3v. 2. average ma supply current. based on 8 ms report rate, except for ma120. [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 5 of 33 figure 3. psoc designer subsystems psoc designer software subsystems device editor the device editor subsystem allows the user to select different onboard analog and digital components called user modules using the psoc blocks. examples of user modules are adcs, dacs, amplifiers, and filters. the device editor also supports easy development of multiple configurations and dynamic rec onfiguration. dy namic configu- ration allows changing configurations at run time. psoc designer sets up power-on initialization tables for selected psoc block configurations and creates source code for an appli- cation framework. the framework contains software to operate the selected components. if the project uses more than one operating configuration, then it contains routines to switch between different sets of psoc block configurations at run time. psoc designer prints out a configuration sheet for a given project configuration for use during application programming in conjunction with the device data sheet. after the framework is generated, the user can add applic ation-specific code to flesh out the framework. it is also possible to change the selected components and regenerate the framework. design browser the design browser allows users to select and import precon- figured designs into the user?s project. users can easily browse a catalog of preconfigured designs to facilitate time-to-design. examples provided in the tools include a 300-baud modem, lin bus master and slave, fan controlle r, and magnetic card reader. application editor in the application editor you can edit your c language and assembly language source code. you can also assemble, compile, link, and build. assembler. the macro assembler allows the assembly code to be merged seamlessly with c code. the link libraries automati- cally use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing. c language compiler. a c language compiler is available that supports the psoc family of devices. even if you have never worked in the c language before, t he product quickly allows you to create complete c programs for the psoc family devices. the embedded, optimizing c compiler provides all the features of c tailored to the psoc architecture. it comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger the psoc designer debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow the designer to read and program and read and write data memory, read and write io registers, read and write cpu r egisters, set and clear break- points, and provide program run, halt, and step control. the debugger also allows the designer to create a trace buffer of registers and memory lo cations of interest. online help system the online help system displays online, context-sensitive help for the user. designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. this system also provides tutorials and links to faqs and an online support forum to aid the designer in getting started. hardware tools in-circuit emulator a low cost, high functionality ice is available for development support. this hardware has the capability to program single devices. the emulator consists of a base unit that connects to the pc by way of a usb port. the base unit is universal and operates with all psoc devices. emulation p ods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full speed (24 mhz) operation. truetouch touchscreen tuner the truetouch tuner is a microsoft ? windows based graphical user interface allowing developer s to set critical parameters and observe changes to the touchscreen application in real time. optimal configuration from the tuner can be immediately applied to the truetouch user module settings. commands results psoc designer core engine psoc configuration sheet manufacturing information file device database importable design database device programmer graphical designer interface context sensitive help emulation pod in-circuit emulator project database application database user modules library psoc designer [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 6 of 33 designing with user modules the development process for the psoc device differs from that of a traditional fixed function microprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and by lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variety of user-selectable functions. each block has severa l registers that determine its function and connectivity to other blocks, mu ltiplexers, buses and to the io pins. iterative development cycl es permit you to adapt the hardware and software. this su bstantially lowers the risk of having to select a different part to meet the final design require- ments. to speed the development process, the psoc designer ide provides a library of pre-built, pre-tested hardware peripheral functions, called ?user modules. ? user modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. the standard user module library contains over 50 common peripherals such as adcs, dacs timers, counters, uarts, and other not so common peripherals such as dtmf generators and bi-quad analog filter sections. each user module establishes t he basic register settings that implement the selected function. it also provides parameters that allow you to tailor its precise configuration to your particular application. for example, a pulse width modulator user module configures one or more digital psoc blocks, one for each 8 bits of resolution. the user module parameters permit to establish the pulse width and duty cycle. us er modules also provide tested software to cut development time. the user module application programming interface (api) provides high level functions to control and respond to hardware events at run-time. the api also provides optional interrupt service routines that are adapted as needed. the api functions are document ed in user module data sheets that are viewed directly in the psoc designer ide. these data sheets explain the internal operation of the user module and provide performance specificatio ns. each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module. the development process starts when you open a new project and bring up the device editor, a graphical user interface (gui) for configuring the hardware. pick the user modules you need for your project and map them onto the psoc blocks with point-and-click simplici ty. next, build signal chains by intercon- necting user modules to each other and the io pins. at this stage, also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. when you are ready to test the hardware configuration or move on to developing code for the project, perform the ?generate application? step. this causes psoc designer to generate source code that automatically configures the device to your specification and provides the high level user module api functions. figure 4. user module and source code development flows the next step is to write your main program, and any sub-routines using psoc designer?s application editor subsystem. the application edit or includes a project manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. the source code editor provides syntax coloring and advanced edit features for both c and assembly language. file search capabilities include simple string searches and recursive ?grep-style? patterns. a single mouse click invokes the build manager. it employs a professional strength ?m akefile? system to automatically analyze all file dependencies and run the compiler and assembler as necessary. project level options control optimizat ion strategies used by the compiler and linker. syntax errors are displayed in a console window. double click the error message to view the offending line of source code. when all is correct, the linker builds a hex file image suitable for programming. the last step in the development process takes place inside the psoc designer?s debugger subsystem. the debugger downloads the hex image to the ic e where it runs at full speed. debugger capabilities rival those of systems costing many times more. in addition to traditional single-step, run-to-breakpoint and watch-variable features, the d ebugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. debugger interface to ice application editor device editor project manager source code editor storage inspector user module selection placement and parameter -ization generate application build all event & breakpoint manager build manager source code generator [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 7 of 33 document conventions acronyms used the following table lists the acronyms that are used in this document. units of measure a units of measure table is locat ed in the electrical specifications section. table 4 on page 11 lists all the abbreviations used to measure the psoc devices. numeric naming hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? prefix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicated by an ?h?, ?0x?, or ?b? are decimal. acronym description ac alternating current adc analog-to-digital converter api application programming interface cpu central processing unit ct continuous time dac digital-to-analog converter dc direct current eco external crystal oscillator eeprom electrically erasable programmable read-only memory fsr full scale range gpio general purpose io gui graphical user interface hbm human body model ice in-circuit emulator ilo internal low speed oscillator imo internal main oscillator io input/output ipor imprecise power on reset lsb least-significant bit lvd low voltage detect msb most-significant bit pc program counter pll phase-locked loop por power on reset ppor precision power on reset psoc? programmable system-on-chip? pwm pulse width modulator sc switched capacitor sram static random access memory [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 8 of 33 pinouts this section describes, lists, and illustrates the CY8CTMG120 truetouch family pins and pinou t configuration. the CY8CTMG120 truetouch device is available in the following packages, all of which are shown on the following pages. every port pin (labeled with a ?p?) is capable of digital io. however, vss, vdd, and xres are not capable of digital io. 56-pin part pinout table 2. 56-pin part pinout (qfn) pin no. type name description figure 5. CY8CTMG120 56-pin psoc device digital analog 1 io i, m p2[3] direct switched capacitor block input. 2 io i, m p2[1] direct switched capacitor block input. 3 io mp4[7] 4 io mp4[5] 5 io mp4[3] 6 io mp4[1] 7 io mp3[7] 8 io mp3[5] 9 io mp3[3] 10 io mp3[1] 11 io m p5[7] 12 io m p5[5] 13 io mp5[3] 14 io mp5[1] 15 io m p1[7] i2c serial clock (scl). 16 io m p1[5] i2c serial data (sda). 17 io m p1[3] 18 io m p1[1] i2c serial clock (scl), issp sclk [3] . 19 power vss ground. connect to circuit ground. 20 usb d+ 21 usb d- 22 power vdd supply voltage. bypass to ground with 0.1 uf capacitor. 23 io p7[7] 24 io p7[0] 25 io m p1[0] i2c serial data (sda), issp sdata [3] . 26 io m p1[2] 27 io mp1[4] 28 io mp1[6] 29 io mp5[0] pin no. type name description 30 io mp5[2] digital analog 31 io m p5[4] 44 io m p2[6] external voltage reference (vref) input. 32 io m p5[6] 45 io i, m p0[0] analog column mux input. 33 io mp3[0] 46 io i, m p0[2] analog column mux input. 34 io mp3[2] 47 io i, m p0[4] analog column mux input vref. 35 io m p3[4] 48 io i, m p0[6] analog column mux input. 36 input xres active high external reset with internal pull down. 49 power vdd supply voltage. bypass to ground with 0.1 uf capacitor. 37 io mp4[0] 50 power vss ground. connect to circuit ground. 38 io mp4[2] 51 io i, m p0[7] analog column mux input,. 39 io m p4[4] 52 io io, m p0[5] analog column mux input and column output. 40 io m p4[6] 53 io io, m p0[3] analog column mux input and column output. 41 io i, m p2[0] direct switched capacitor block input. 54 io i, m p0[1] analog column mux input. 42 io i, m p2[2] direct switched capacitor block input. 55 io m p2[7] 43 io m p2[4] external analog ground (agnd) input. 56 io mp2[5] ep power vss exposed pad is internally connected to ground. connect to circuit ground. legend a = analog, i = input, o = output, and m = analog mux input. qfn (top view) a, i, m, p2[3] a, i, m, p2[1] m, p4 [7 ] m, p4 [5 ] m, p4 [3 ] m, p4 [1 ] m, p3 [7 ] m, p3 [5 ] m, p3 [3 ] m, p3 [1 ] m, p5 [7 ] m, p5 [5 ] m, p5 [3 ] m, p5 [1 ] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 m, i2c scl, p1[7] m, i2c sda, p1[5] m, p1[3] m, i2c scl, p1[1] vss d+ d- vdd p7[7] p7[0] m, i2c sda, p1[0] m, p1[2] m, p1[4] m, p1[6] 15 16 17 18 19 20 21 22 23 24 25 26 27 28 p2[4], m p2[6], m p0[0], a, i, m p0[2], a, i, m p0[4], a, i, m p0[6], a, i, m vdd vss p0[7], a, i, m p0[5], a, io, m p0[3], a, io, m p0[1], a, i, m p2[7], m p2[5], m 43 44 45 46 47 48 49 50 51 52 53 54 55 56 p2[2], a, i, m p2[0], a, i, m p4[6], m p4[4], m p4[2], m p4[0], m xr es p3[4], m p3[2], m p3[0], m p5[6], m p5[4], m p5[2], m p5[0], m 42 41 40 39 38 37 36 35 34 33 32 31 30 29 note 3. these are the issp pins, which are not high z at por. [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 9 of 33 100-pin part pinout (on-chip debug) the 100-pin tqfp part is the CY8CTMG120 on-chip debug (ocd) truetouch device. note this part is only used for in-circuit debugging. it is not available for production. figure 6. CY8CTMG120 ocd table 3. 100-pin part pinout (tqfp) pin no. digital analog name description pin no. digital analog name description 1 nc no connection. leave floating. 51 io mp1[6] 2 nc no connection. leave floating. 52 io mp5[0] 3 io i, m p0[1] analog column mux input. 53 io mp5[2] 4 io m p2[7] 54 io m p5[4] 5 io m p2[5] 55 io m p5[6] 6 io i, m p2[3] direct switched capacitor block input. 56 io mp3[0] 7 io i, m p2[1] direct switched capacitor block input. 57 io mp3[2] 8 io m p4[7] 58 io m p3[4] 9 io m p4[5] 59 io m p3[6] 10 io m p4[3] 60 hclk ocd high-speed clock output. 11 io m p4[1] 61 cclk ocd cpu clock output. 12 ocde ocd even data io. 62 input xres active high pin reset with internal pull down. 13 ocd o ocd odd data output. 63 io m p4[0] 14 nc no connection. leave floating. 64 io mp4[2] 15 power vss ground. connect to circuit ground. 65 power vss ground. connect to circuit ground. 16 io m p3[7] 66 io m p4[4] 17 io m p3[5] 67 io m p4[6] tqfp nc nc ai, m, p0[1] m, p2[7] m, p2[5] ai, m, p2[3] ai, m, p2[1] m, p4[7] m, p4[5] m, p4[3] m, p4[1] ocde ocdo nc vss m, p3[7] m, p3[5] m, p3[3] m, p3[1] m, p5[7] m, p5[5] m, p5[3] m, p5[1] i2c scl, p1[7] nc nc d- p7[3] nc nc i2c sda, m, p1[5] m, p1[3] i2c scl, m, p1[1] nc vss d+ vdd p7[7] p7[6] p7[5] p7[4] p7[2] p7[1] p7[0] nc nc nc i2c sda, m, p1[0] m, p1[2] m, p1[4] nc p0[0], m, ai nc p2[6], m, external vref nc p2[4], m, external agnd p2[2], m, ai p2[0], m, ai p4[6], m p4[4], m vss p4[2], m p4[0], m xres cclk hclk p3[6], m p3[4], m p3[2], m p3[0], m p5[6], m p5[4], m p5[2], m p5[0], m p1[6], m nc p0[3], m, ai nc p0[5], m, ai nc p0[7], m, ai nc nc nc nc nc nc nc nc nc nc vss nc vdd p0[6], m, ai nc p0[4], m, ai nc p0[2], m, ai nc 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 50 49 [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 10 of 33 pin no. digital analog name description pin no. digital analog name description 19 io m p3[1] 69 io i, m p2[2] direct switched capacitor block input. 20 io m p5[7] 70 io p2[4] external analog ground (agnd) input. 21 io m p5[5] 71 nc no connection. leave floating. 22 io m p5[3] 72 io p2[6] external voltage reference (vref) input. 23 io m p5[1] 73 nc no connection. leave floating. 24 io m p1[7] i2c serial clock (scl). 74 io i p0[0] analog column mux input. 25 nc no connection. leave floating. 75 nc no connection. leave floating. 26 nc no connection. leave floating. 76 nc no connection. leave floating. 27 nc no connection. leave floating. 77 io i, m p0[2] analog column mux input and column output. 28 io p1[5] i2c serial data (sda) 78 nc no connection. leave floating. 29 io p1[3] 79 io i, m p0[4] analog column mux input and column output. 30 io p1[1] crystal (xtalin), i2c serial clock (scl), issp sclk [3] . 80 nc no connection. leave floating. 31 nc no connection. leave floating. 81 io i, m p0[6] analog column mux input. 32 power vss ground. connect to circuit ground. 82 power vdd supply voltage. bypass to ground with 0.1 uf capacitor. 33 usb d+ 83 nc no connection. leave floating. 34 usb d- 84 power vss ground. connect to circuit ground. 35 power vdd supply voltage. bypass to ground with 0.1 uf capacitor. 85 nc no connection. leave floating. 36 io p7[7] 86 nc no connection. leave floating. 37 io p7[6] 87 nc no connection. leave floating. 38 io p7[5] 88 nc no connection. leave floating. 39 io p7[4] 89 nc no connection. leave floating. 40 io p7[3] 90 nc no connection. leave floating. 41 io p7[2] 91 nc no connection. leave floating. 42 io p7[1] 92 nc no connection. leave floating. 43 io p7[0] 93 nc no connection. leave floating. 44 nc no connection. leave floating. 94 nc no connection. leave floating. 45 nc no connection. leave floating. 95 io i, m p0[7] analog column mux input. 46 nc no connection. leave floating. 96 nc no connection. leave floating. 47 nc no connection. leave floating. 97 io io, m p0[5] analog column mux input and column output. 48 io p1[0] crystal (xtalout), i2c serial data (sda), issp sdata [3] . 98 nc no connection. leave floating. 49 io p1[2] 99 io io, m p0[3] analog column mux input and column output. 50 io p1[4] optional external clock input (extclk). 100 nc no connection. leave floating. legend a = analog, i = input, o = output, nc = no connec tion, m = analog mux input, ocd = on-chip debugger. table 3. 100-pin part pinout (tqfp) (continued) [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 11 of 33 electrical specifications this section presents the dc and ac electric al specifications of the cy 8ctmg120 truetouch device family. for the most up to dat e electrical specifications, confirm that you have t he most recent data sheet by going to the web at http://www.cypress.com/psoc. specifications are valid for -40 o c t a 85 o c and t j 100 o c, except where noted. specifications for devices running at greater than 12 mhz are valid for -40 o c t a 70 o c and t j 82 o c. figure 7. voltage versus cpu frequency ta b l e 4 lists the units of measure t hat are used in this section table 4. units of measure symbol unit of measure symbol unit of measure o c degree celsius w microwatts db decibels ma milli-ampere ff femto farad ms milli-second hz hertz mv milli-volts kb 1024 bytes na nanoampere kbit 1024 bits ns nanosecond khz kilohertz nv nanovolts k kilohm ohm mhz megahertz pa picoampere m megaohm pf picofarad a microampere pp peak-to-peak f microfarad ppm parts per million h microhenry ps picosecond s microsecond sps samples per second v microvolts s sigma: one standard deviation vrms microvolts root-mean-square v volts 5.25 4.75 3.00 93 khz 12 mhz 24 mhz cpu frequency vdd voltage v a l i d o p e r a t i n g r e g i o n [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 12 of 33 absolute maximum ratings operating temperature table 5. absolute maximum ratings symbol description min typ max units notes t stg storage temperature -55 25 +100 o c higher storage temperatures reduces data retention time. recommended storage temper- ature is +25 o c 25 o c. extended duration storage temperatures above 65 o c degrades reliability. t a ambient temperature with power applied -40 ? +85 o c vdd supply voltage on vdd relative to vss -0.5 ? +6.0 v v io dc input voltage vss - 0.5 ? vdd + 0.5 v v io2 dc voltage applied to tri-state vss - 0.5 ? vdd + 0.5 v i mio maximum current in to any port pin -25 ? +50 ma i maio maximum current in to any port pin configured as analog driver -50 ? +50 ma esd electro static discharge voltage [4] . 2000 ? ? v human body model esd. lu latch up current ? ? 200 ma table 6. operating temperature symbol description min typ max units notes t a ambient temperature [5] . -40 ? +85 o c t ausb ambient temperature using usb -10 ? +85 o c t j junction temperature -40 ? +100 o c the temperature rise from ambient to junction is package specific. see thermal impedance for the package on page 30. the user must limit the power consumption to comply with this requirement. notes 4. see the user module data sheet for touchscreen application related esd testing 5. see the user module data sheet for touchscr een application related temperature testing. [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 13 of 33 dc electrical characteristics the below electrical characteristics are fo r proper cpu core and i/o operation. for capacitive touchscreen electrical character istics, refer to the touchscreen user module data sheet. dc chip level specifications ta b l e 7 lists guaranteed maximum and minimum specifications for th e voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c. these are for design guidance only. table 7. dc chip level specifications symbol description min typ max units notes vdd supply voltage 3.0 ? 5.25 v see dc por and lvd specifications, table 19 on page 20. i dd5 supply current, imo = 24 mhz (5v) ? 14 27 ma conditions are vdd = 5.0v, t a = 25 o c, cpu = 3 mhz, sysclk doubler disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 93.75 khz, analog power = off. i dd3 supply current, imo = 24 mhz (3.3v) ? 8 14 ma conditions are vdd = 3.3v, t a = 25 o c, cpu = 3 mhz, sysclk doubler disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 0.367 khz, analog power = off. i sb sleep (mode) current with por, lvd, sleep timer, and wdt. [6] . ? 3 6.5 a conditions are with internal slow speed oscillator, vdd = 3.3v, -40 o c t a 55 o c, analog power = off. i sbh sleep (mode) current with por, lvd, sleep timer, and wdt at high temperature. [6] . ? 4 25 a conditions are with internal slow speed oscillator, vdd = 3.3v, 55 o c < t a 85 o c, analog power = off. note 6. standby current includes all functions (por, lvd, wdt, sleep time) needed for reliable system operation. this should be compa red with devices that have similar functions enabled. [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 14 of 33 dc general purpose io specifications ta b l e 8 lists guaranteed maximum and minimum specifications for th e voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c. these are for design guidance only. dc full-speed usb specifications ta b l e 9 lists guaranteed maximum and minimum specifications for th e voltage and temperature ranges: 4.75v to 5.25v and -10 c t a 85 c, or 3.0v to 3.6v and -10 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c. these are for design guidance only. table 8. dc gpio specifications symbol description min typ max units notes r pu pull up resistor 4 5.6 8 k r pd pull down resistor 4 5.6 8 k v oh high output level vdd - 1.0 ? ? v ioh = 10 ma, vdd = 4.75 to 5.25v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). 80 ma maximum combined ioh budget. v ol low output level ? ? 0.75 v iol = 25 ma, vdd = 4.75 to 5.25v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). 200 ma maximum combined iol budget. v il input low level ? ? 0.8 v vdd = 3.0 to 5.25. v ih input high level 2.1 ? v vdd = 3.0 to 5.25. v h input hysterisis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. temp = 25 o c. c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. temp = 25 o c. table 9. dc full speed (12 mbps) usb specifications symbol description min typ max units notes usb interface v di differential input sensitivity 0.2 ? ? v | (d+) - (d-) | v cm differential input common mode range 0.8 ? 2.5 v v se single ended receiver threshold 0.8 ? 2.0 v c in transceiver capacitance ? ? 20 pf i io high-z state data line leakage -10 ? 10 a0v < v in < 3.3v. r ext external usb series resistor 23 ? 25 w in series with each usb pin. v uoh static output high, driven 2.8 ? 3.6 v 15 k 5% to ground. internal pull-up enabled. v uohi static output high, idle 2.7 ? 3.6 v 15 k 5% to ground. internal pull-up enabled. v uol static output low ? ? 0.3 v 15 k 5% to ground. internal pull-up enabled. z o usb driver output impedance 28 ? 44 w including r ext resistor. v crs d+/d- crossover voltage 1.3 ? 2.0 v [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 15 of 33 dc operational amplifier specifications ta b l e 1 0 and ta b l e 11 list guaranteed maximum and minimum specifications fo r the voltage and temperatur e ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c. these are for design guidance only. the operational amplifier is a component of both the analog co ntinuous time psoc blocks and the analog switched capacitor psoc blocks. the guaranteed sp ecifications are measured in the a nalog continuous time psoc block. table 10. 5v dc operatio nal amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ?1.6 1.3 1.2 10 8 7.5 mv mv mv tcv osoa average input offset voltage drift ? 7.0 35.0 v/ o c i eboa input leakage current (port 0 analog pins) ? 20 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. te m p = 2 5 o c. v cmoa common mode voltage range common mode voltage range (high power or high opamp bias) 0.0 ? vdd vdd - 0.5 v the common-mode input voltage range is measured through an analog output buffer. the specifi- cation includes the limitations imposed by the characteristics of the analog output buffer. 0.5 ? g oloa open loop gain power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high 60 60 80 ?? db v ohighoa high output voltage swing (internal signals) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high vdd - 0.2 vdd - 0.2 vdd - 0.5 ? ? ? ? ? ? v v v v olowoa low output voltage swing (internal signals) power = low, opamp bias = high power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 0.2 0.2 0.5 v v v i soa supply current (including associated agnd buffer) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 400 500 800 1200 2400 4600 800 900 1000 1600 3200 6400 a a a a a a psrr oa supply voltage rejection ratio 65 80 ? db vss vin (vdd - 2.25) or (vdd - 1.25v) vin vdd. [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 16 of 33 table 11. 3.3v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltag e (absolute value) power = low, opamp bias = high power = medium, opamp bias = high high power is 5v only ? ? 1.65 1.32 10 8 mv mv tcv osoa average input offset voltage drift ? 7.0 35.0 v/ o c i eboa input leakage current (port 0 analog pins) ? 20 ? pa gross tested to 1 a. c inoa input capacitance (port 0 analog pins ) ? 4.5 9.5 pf package and pin dependent. te m p = 2 5 o c. v cmoa common mode voltage range 0.2 ? vdd - 0.2 v the common-mode input voltage range is measured through an analog output buffer. the specification includes the limitations imposed by the characteristics of the analog output buffer. g oloa open loop gain power = low, opamp bias = low power = medium, opamp bias = low power = high, opamp bias = low 60 60 80 ?? db v ohighoa high output voltage swing (internal signals) power = low, opamp bias = low power = medium, opamp bias = low power = high is 5v only vdd - 0.2 vdd - 0.2 vdd - 0.2 ? ? ? ? ? ? v v v v olowoa low output voltage swing (internal signals) power = low, opamp bias = low power = medium, opamp bias = low power = high, opamp bias = low ? ? ? ? ? ? 0.2 0.2 0.2 v v v i soa supply current (including associated agnd buffer) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 400 500 800 1200 2400 4600 800 900 1000 1600 3200 6400 a a a a a a psrr oa supply voltage rejection ratio 65 80 ? db vss vin (vdd - 2.25) or (vdd - 1.25v) vin vdd. [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 17 of 33 dc low power comparator specifications ta b l e 1 2 lists guaranteed maximum and minimum specifications for th e voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v at 25 c. these are for design guidance only. dc idac resolution ta b l e 1 3 lists idac typical resolution. typical parameters apply to 5v at 25 c. these are for design guidance only. dc analog output bu ffer specifications ta b l e 1 4 and ta b l e 1 5 list guaranteed maximum and minimum specifications for the voltage and temperatur e ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c. these are for design guidance only. table 12. dc low power comparator specifications symbol description min typ max units notes v reflpc low power comparator (lpc) reference voltage range 0.2 ? vdd - 1 v i slpc lpc supply current ? 10 40 a v oslpc lpc voltage offset ? 2.5 30 mv table 13. dc low power comparator specifications symbol description min typ max units notes i dac current output of 1 lsb (1x setting) - 75 - na table 14. 5v dc analog output buffer specifications symbol description min typ max units notes v osob input offset voltage (absolute value) ? 3 12 mv tcv oso b average input offset voltage drift ? +6 ? v/c v cmob common-mode input voltage range 0.5 ? vdd - 1.0 v r outob output resistance power = low power = high ? ? 0.6 0.6 ? ? w w v ohigho b high output voltage swing (load = 32 ohms to vdd/2) power = low power = high 0.5 x vdd + 1.1 0.5 x vdd + 1.1 ? ? ? ? v v v olowob low output voltage swing (load = 32 ohms to vdd/2) power = low power = high ? ? ? ? 0.5 x vdd - 1.3 0.5 x vdd - 1.3 v v i sob supply current including bias cell (no load) power = low power = high ? ? 1.1 2.6 5.1 8.8 ma ma psrr ob supply voltage rejection ratio 53 64 ? db (0.5 x vdd - 1.3) v out (vdd - 2.3). [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 18 of 33 dc analog reference specifications ta b l e 1 6 and ta b l e 1 7 list guaranteed maximum and minimum specifications for the voltage and temperatur e ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c. these are for design guidance only. the guaranteed specifications are measured through the analog continuous time psoc blocks. the power levels for agnd refer to the power of the analog continuous time pso c block. the power levels for refhi and reflo refer to the analog reference control register. the limits stated for agnd include the offset error of the agnd buffer local to the analog continuous time psoc block . reference control power is high. table 15. 3.3v dc analog output buffer specifications symbol description min typ max units notes v osob input offset voltage (absolute value) ? 3 12 mv tcv osob average input offset voltage drift ? +6 ? v/c v cmob common-mode input voltage range 0.5 - vdd - 1.0 v r outob output resistance power = low power = high ? ? 1 1 ? ? w w v ohighob high output voltage swing (load = 1k ohms to vdd/2) power = low power = high 0.5 x vdd + 1.0 0.5 x vdd + 1.0 ? ? ? ? v v v olowob low output voltage swing (load = 1k ohms to vdd/2) power = low power = high ? ? ? ? 0.5 x vdd - 1.0 0.5 x vdd - 1.0 v v i sob supply current including bias cell (no load) power = low power = high ? 0.8 2.0 2.0 4.3 ma ma psrr ob supply voltage rejection ratio 34 64 ? db (0.5 x vdd - 1.0) v out (0.5 x vdd + 0.9). table 16. 5v dc analog reference specifications symbol description min typ max units bg bandgap voltage reference 1.28 1.30 1.32 v ? agnd = vdd/2 [7] vdd/2 - 0.04 vdd/2 - 0.01 vdd/2 + 0.007 v ? agnd = 2 x bandgap [7] 2 x bg - 0.048 2 x bg - 0.030 2 x bg + 0.024 v ? agnd = p2[4] (p2[4] = vdd/2) [7] p2[4] - 0.011 p2[4] p2[4] + 0.011 v ? agnd = bandgap [7] bg - 0.009 bg + 0.008 bg + 0.016 v ? agnd = 1.6 x bandgap [7] 1.6 x bg - 0.022 1.6 x bg - 0.010 1.6 x bg + 0.018 v ? agnd block to block variation (agnd = vdd/2) [7] -0.034 0.000 0.034 v ? refhi = vdd/2 + bandgap vdd /2 + bg - 0.10 vdd /2 + bg vdd /2 + bg + 0.10 v ? refhi = 3 x bandgap 3 x bg - 0.06 3 x bg 3 x bg + 0.06 v ? refhi = 2 x bandgap + p2[6] (p2[6] = 1.3v) 2 x bg + p2[6] - 0.113 2 x bg + p2[6] - 0.018 2 x bg + p2[6] + 0.077 v ? refhi = p2[4] + bandgap (p2[4] = vdd/2) p2[4] + bg - 0.130 p2[4] + bg - 0.016 p2[4] + bg + 0.098 v ? refhi = p2[4] + p2[6] (p2[4] = vdd/2, p2[6] = 1.3v) p2[4] + p2[6] - 0.133 p2[4] + p2[6] - 0.016 p2[4] + p2[6]+ 0.100 v note 7. agnd tolerance includes the offsets of the local buffer in the psoc block. bandgap voltage is 1.3v 0.02v. [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 19 of 33 ? refhi = 3.2 x bandgap 3.2 x bg - 0.112 3.2 x bg 3.2 x bg + 0.076 v ? reflo = vdd/2 ? bandgap vdd /2 - bg - 0.04 vdd /2 - bg + 0.024 vdd /2 - bg + 0.04 v ? reflo = bandgap bg - 0.06 bg bg + 0.06 v ? reflo = 2 x bandgap - p2[6] (p2[6] = 1.3v) 2 x bg - p2[6] - 0.084 2 x bg - p2[6] + 0.025 2 x bg - p2[6] + 0.134 v ? reflo = p2[4] ? bandgap (p2[4] = vdd/2) p2[4] - bg - 0.056 p2[4] - bg + 0.026 p2[4] - bg + 0.107 v ? reflo = p2[4]-p2[6] (p2[4] = vdd/2, p2[6] = 1.3v) p2[4] - p2[6] - 0.057 p2[4] - p2[6] + 0.026 p2[4] - p2[6] + 0.110 v table 16. 5v dc analog reference specifications (continued) symbol description min typ max units table 17. 3.3v dc analog reference specifications symbol description min typ max units bg bandgap voltage reference 1.28 1.30 1.32 v ? agnd = vdd/2 [7] vdd/2 - 0.03 vdd/2 - 0.01 vdd/2 + 0.005 v ? agnd = 2 x bandgap [7] not allowed ? agnd = p2[4] (p 2[4] = vdd/2) p2[4] - 0.008 p2[4] + 0.001 p2[4] + 0.009 v ? agnd = bandgap [7] bg - 0.009 bg + 0.005 bg + 0.015 v ? agnd = 1.6 x bandgap [7] 1.6 x bg - 0.027 1.6 x bg - 0.010 1.6 x bg + 0.018 v ? agnd column to column variation (agnd = vdd/2) [7] -0.034 0.000 0.034 v ? refhi = vdd/2 + bandgap not allowed ? refhi = 3 x bandgap not allowed ? refhi = 2 x bandgap + p2[6] (p2[6] = 0.5v) not allowed ? refhi = p2[4] + bandgap (p2[4] = vdd/2) not allowed ? refhi = p2[4] + p2[6] (p2[4] = vdd/2, p2[6] = 0.5v) p2[4] + p2[6] - 0.075 p2[4] + p2[6] - 0.009 p2[4] + p2[6] + 0.057 v ? refhi = 3.2 x bandgap not allowed ? reflo = vdd/2 - bandgap not allowed ? reflo = bandgap not allowed ? reflo = 2 x bandgap - p2[6] (p2[6] = 0.5v) not allowed ? reflo = p2[4] ? bandgap (p2[4] = vdd/2) not allowed ? reflo = p2[4]-p2[6] (p2[4] = vdd/2, p2[6] = 0.5v) p2[4] - p2[6] - 0.048 p2[4]- p2[6] + 0.022 p2[4] - p2[6] + 0.092 v [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 20 of 33 dc analog psoc block specifications ta b l e 1 8 lists guaranteed maximum and minimum specifications for th e voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c. these are for design guidance only. dc por and lvd specifications ta b l e 1 9 lists guaranteed maximum and minimum specifications for th e voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v or 3.3v at 25 c. these are for design guidance only. note the bits porlev and vm in the table below refer to bits in the vlt_cr register. table 18. dc analog psoc block specifications symbol description min typ max units notes r ct resistor unit value (continuous time) ? 12.2 ? k c sc capacitor unit value (switched capacitor) ? 80 ? ff table 19. dc por and lvd specifications symbol description min typ max units notes v ppor0r v ppor1r v ppor2r vdd value for ppor trip (positive ramp) porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? 2.91 4.39 4.55 ? v v v v ppor0 v ppor1 v ppor2 vdd value for ppor trip (negative ramp) porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? 2.82 4.39 4.55 ? v v v v ph0 v ph1 v ph2 ppor hysteresis porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? ? ? 92 0 0 ? ? ? mv mv mv v lvd0 v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 vdd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 2.98 [8] 3.08 3.20 4.08 4.57 4.74 [9] 4.82 4.91 v v v v v v v v notes 8. always greater than 50 mv above ppor (porlev = 00) for falling supply. 9. always greater than 50 mv above ppor (porlev = 10) for falling supply. [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 21 of 33 dc programming specifications ta b l e 2 0 lists guaranteed maximum and minimum specifications for th e voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c. these are for design guidance only. table 20. dc programming specifications symbol description min typ max units notes i ddp supply current during programming or verify ? 15 30 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.1 ? ? v i ilp input current when applying vilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull-down resistor. i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull-down resistor. v olv output low voltage during programming or verify ? ? vss + 0.75 v v ohv output high voltage during programming or verify vdd - 1.0 ? vdd v flash enp b flash endurance (per block) 50,000 ? ? ? erase/write cycles per block. flash ent flash endurance (total) [10] 1,800,000 ? ? ? erase/write cycles. flash dr flash data retention 10 ? ? years note 10. a maximum of 36 x 50,000 block endurance cycles is allowed. th is may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blo cks of 12,500 maximum cycles eac h (to limit the total number of cycles to 36x50,000 a nd that no single block ever sees more than 50,000 cycles). for the full industrial range, the user must employ a temperatur e sensor user module (flashtemp) and feed the result to the tem perature argument before writing. refer to the flash apis application note an2015 at http://www.cypress.com under application notes for more information. [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 22 of 33 ac electrical characteristics ac chip level specifications ta b l e 2 1 lists guaranteed maximum and minimum specifications for th e voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c. these are for design guidance only. figure 8. 24 mhz period jitter (imo) timing diagram table 21. ac chip level specifications symbol description min typ max units notes f imo245v internal main oscillat or frequency for 24 mhz (5v) 23.04 24 24.96 [11,12] mhz trimmed for 5v operation using factory trim values. f imo243v internal main oscillat or frequency for 24 mhz (3.3v) 22.08 24 25.92 [12, 13] mhz trimmed for 3.3v operation using factory trim values. f imousb5v internal main oscillator frequency with usb (5v) frequency locking enabled and usb traffic present. 23.94 24 24.06 [12] mhz -10 c t a 85 c 4.35 vdd 5.15 f imousb3v internal main oscillator frequency with usb (3.3v) frequency locking enabled and usb traffic present. 23.94 24 24.06 [12] mhz -0 c t a 70 c 3.15 vdd 3.45 f cpu1 cpu frequency (5v nominal) 0.93 24 24.96 [11, 12] mhz f cpu2 cpu frequency (3.3v nominal) 0.93 12 12.96 [12, 13] mhz f blk5 digital psoc block frequency (5v nominal) 0 48 49.92 [11, 12, 14] mhz refer to the ac digital block speci- fications. f blk3 digital psoc block frequency (3.3v nominal) 0 24 25.92 [12, 14] mhz f 32k1 internal low speed oscillator frequency 15 32 64 khz jitter32k 32 khz period jitter ? 100 ns step24m 24 mhz trim step size ? 50 ? khz fout48m 48 mhz output frequency 46.08 48.0 49.92 [11, 13] mhz trimmed. utilizing factory trim values. jitter24m1 24 mhz period jitter (imo) peak-to-peak ? 300 ps f max maximum frequency of signal on row input or row output. ? ? 12.96 mhz t ramp supply ramp time 0 ? ? s jitter24m1 f 24m notes 11. 4.75v < vdd < 5.25v. 12. accuracy derived from internal main oscillator with appropriate trim for vdd range. 13. 3.0v < vdd < 3.6v. see application note an2012 ?adjusting psoc mi crocontroller trims for dual voltage-range operation? for i nformation on trimming for operation at 3.3v. 14. see the individual user module data sheets for information on maximum frequencies for user modules. [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 23 of 33 ac general purpose io specifications ta b l e 2 2 lists guaranteed maximum and minimum specifications for th e voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c. these are for design guidance only. figure 9. gpio timing diagram ac full-speed usb specifications ta b l e 2 3 lists guaranteed maximum and minimum specifications for th e voltage and temperature ranges: 4.75v to 5.25v and -10 c t a 85 c, or 3.0v to 3.6v and -10 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c. these are for design guidance only. table 22. ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns vdd = 4.5 to 5.25v, 10% - 90% tfallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns vdd = 4.5 to 5.25v, 10% - 90% trises rise time, slow strong mode, cload = 50 pf 10 27 ? ns vdd = 3 to 5.25v, 10% - 90% tfalls fall time, slow strong mode, cload = 50 pf 10 22 ? ns vdd = 3 to 5.25v, 10% - 90% tfallf tf alls trisef trises 90% 10% gpio pin output voltage table 23. ac full-speed (12 mbps) usb specifications symbol description min typ max units notes t rfs transition rise time 4 ? 20 ns for 50 pf load. t fss transition fall time 4 ? 20 ns for 50 pf load. t rfmfs rise/fall time matching: (t r /t f )90 ? 111 % for 50 pf load. t dratef s full-speed data rate 12 - 0.25% 12 12 + 0.25% mbps [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 24 of 33 ac operational amplifier specifications ta b l e 2 4 and ta b l e 2 5 list guaranteed maximum and minimum specifications for the voltage and temperatur e ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c. these are for design guidance only. settling times, slew rates, and gain bandwidth ar e based on the analog continuous time psoc block. power = high and opamp bias = high is not supported at 3.3v . table 24. 5v ac operatio nal amplifier specifications symbol description min typ max units t roa rising settling time from 80% of v to 0.1% of v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 3.9 0.72 0.62 s s s t soa falling settling time from 20% of v to 0.1% of v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 5.9 0.92 0.72 s s s sr roa rising slew rate (20% to 80%)(10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.15 1.7 6.5 ? ? ? ? ? ? v/ s v/ s v/ s sr foa falling slew rate (20% to 80%)(10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.01 0.5 4.0 ? ? ? ? ? ? v/ s v/ s v/ s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.75 3.1 5.4 ? ? ? ? ? ? mhz mhz mhz e noa noise at 1 khz (power = medium , opamp bias = high) ? 100 ? nv/rt-h z table 25. 3.3v ac operational amplifier specifications symbol description min typ max units t roa rising settling time from 80% of v to 0.1% of v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high ? ? ? ? 3.92 0.72 s s t soa falling settling time from 20% of v to 0.1% of v (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high ? ? ? ? 5.41 0.72 s s sr roa rising slew rate (20% to 80%)(10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.31 2.7 ? ? ? ? v/ s v/ s sr foa falling slew rate (20% to 80%)(10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high 0.24 1.8 ? ? ? ? v/ s v/ s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high 0.67 2.8 ? ? ? ? mhz mhz e noa noise at 1 khz (power = medium, opamp bias = high) ? 100 ? nv/rt-hz [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 25 of 33 ac low power comparator specifications ta b l e 2 6 lists guaranteed maximum and minimum specifications for th e voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v at 25 c. these are for design guidance only. ac digital block specifications ta b l e 2 7 lists guaranteed maximum and minimum specifications for th e voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c. these are for design guidance only. table 26. ac low power comparator specifications symbol description min typ max units notes t rlpc lpc response time ? ? 50 s 50 mv overdrive comparator reference set within v reflpc . table 27. ac digital block specifications function description min typ max units notes timer capture pulse width 50 [15] ? ? ns maximum frequency, no capture ? ? 49.92 mhz 4.75v < vdd < 5.25v. maximum frequency, with capture ? ? 25.92 mhz counter enable pulse width 50 [15] ? ? ns maximum frequency, no enable input ? ? 49.92 mhz 4.75v < vdd < 5.25v. maximum frequency, enable input ? ? 25.92 mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 50 [15] ? ? ns disable mode 50 [15] ? ? ns maximum frequency ? ? 49.92 mhz 4.75v < vdd < 5.25v. crcprs (prs mode) maximum input clock frequency ? ? 49.92 mhz 4.75v < vdd < 5.25v. crcprs (crc mode) maximum input clock frequency ? ? 24.6 mhz spim maximum input clock frequency ? ? 8.2 mhz maximum data rate at 4.1 mhz due to 2 x over clocking. spis maximum input clock frequency ? ? 4.1 mhz width of ss_ negated between transmis- sions 50 [15] ? ? ns trans- mitter maximum input clock frequency ? ? 24.6 mhz maximum data rate at 3.08 mhz due to 8 x over clocking. receiver maximum input clock frequency ? ? 24.6 mhz maximum data rate at 3.08 mhz due to 8 x over clocking. note 15. 50 ns minimum input pulse width is based on the input synchronizers running at 24 mhz (42 ns nominal period). [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 26 of 33 ac external clock specifications ta b l e 2 8 lists guaranteed maximum and minimum specifications for th e voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c. these are for design guidance only. ac analog output buffer specifications ta b l e 2 9 and ta b l e 3 0 list guaranteed maximum and minimum specifications for the voltage and temperatur e ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c. these are for design guidance only. table 28. ac external clock specifications symbol description min typ max units notes f oscext frequency for usb applications 23.94 24 24.06 mhz ? duty cycle 47 50 53 % ? power up to imo switch 150 ? ? s table 29. 5v ac analog output buffer specifications symbol description min typ max units t rob rising settling time to 0.1%, 1v step, 100pf load power = low power = high ? ? ? ? 2.5 2.5 s s t sob falling settling time to 0.1%, 1v step, 100pf load power = low power = high ? ? ? ? 2.2 2.2 s s sr rob rising slew rate (20% to 80%), 1v step, 100pf load power = low power = high 0.65 0.65 ? ? ? ? v/ s v/ s sr fob falling slew rate (80% to 20%), 1v step, 100pf load power = low power = high 0.65 0.65 ? ? ? ? v/ s v/ s bw obss small signal bandwidth, 20mv pp , 3db bw, 100pf load power = low power = high 0.8 0.8 ? ? ? ? mhz mhz bw obls large signal bandwidth, 1v pp , 3db bw, 100pf load power = low power = high 300 300 ? ? ? ? khz khz table 30. 3.3v ac analog output buffer specifications symbol description min typ max units t rob rising settling time to 0.1%, 1v step, 100pf load power = low power = high ? ? ? ? 3.8 3.8 s s t sob falling settling time to 0.1%, 1v step, 100pf load power = low power = high ? ? ? ? 2.6 2.6 s s sr rob rising slew rate (20% to 80%), 1v step, 100pf load power = low power = high 0.5 0.5 ? ? ? ? v/ s v/ s sr fob falling slew rate (80% to 20%), 1v step, 100pf load power = low power = high 0.5 0.5 ? ? ? ? v/ s v/ s [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 27 of 33 ac programming specifications ta b l e 3 1 lists guaranteed maximum and minimum specifications for th e voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c. these are for design guidance only. bw obss small signal bandwidth, 20mv pp , 3db bw, 100pf load power = low power = high 0.7 0.7 ? ? ? ? mhz mhz bw obls large signal bandwidth, 1v pp , 3db bw, 100pf load power = low power = high 200 200 ? ? ? ? khz khz table 31. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data setup time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t erase b flash erase time (block) ? 10 ? ms t write flash block write time ? 30 ? ms t dsclk data out delay from falling edge of sclk ? ? 45 ns vdd > 3.6 t dsclk3 data out delay from falling edge of sclk ? ? 50 ns 3.0 vdd 3.6 table 30. 3.3v ac analog output buffer specifications (continued) symbol description min typ max units [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 28 of 33 ac i 2 c specifications ta b l e 3 2 lists guaranteed maximum and minimum specifications for th e voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v and 3.3v at 25 c. these are for design guidance only. figure 10. definition for timing for fast/standard mode on the i 2 c bus table 32. ac characteristics of the i 2 c sda and scl pins for vdd symbol description standard mode fast mode units notes min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2 c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? s t highi2c high period of the scl clock 4.0 ?0.6 ? s t sustai2 c setup time for a repeated start condition 4.7 ?0.6 ? s t hddati2 c data hold time 0 ?0 ? s t sudati2 c data setup time 250 ?100 [16] ?ns t sustoi2 c setup time for stop condition 4.0 ?0.6 ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? s t spi2c pulse width of spikes are suppressed by the input filter. ? ? 0 50 ns sda scl s sr s p t bufi2c t spi2c t hdstai2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c note 16. a fast-mode i2c-bus device can be used in a standard-mode i2c-bus system, but the requirement t su;dat 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl sig nal. if such device does stretch t he low period of the scl signal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i2 c-bus specification) before the scl line is released. [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 29 of 33 packaging information this section illustrates the package specification for the cy8ctm g120 truetouch devices, along with the thermal impedance for t he package and solder reflow peak temperatures. it is important to note that emulation tools may require a lar ger area on the target pcb than th e chip?s footprint. for a detai led description of the emulatio n tools? dimensions, refe r to the document titled psoc emulator pod dimensions at http://www.cypress. com/design/mr10161 . for information on the preferred dimensions for mount ing qfn packages, see the following application note at http://www.amkor.com/products/notes_papers/mlfappnote.pdf . pinned vias for thermal conduction are not required for the low power psoc device. figure 11. 56-lead (8x8 mm) qfn 001-12921 ** [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 30 of 33 figure 12. i100-lead (14x14 x 1.4 mm) tqfp solder reflow peak temperature following is the minimum solder reflow peak temperature to achieve good solderability. thermal impedance for the package package typical ja [17] 56 qfn [18] 12.93 o c/w 100 tqfp 51 o c/w table 33. solder reflow peak temperature package minimum peak temperature [19] maximum peak temperature 56 qfn 240 o c 260 o c 51-85048 *c notes 17. t j = t a + power x ja. 18. to achieve the thermal impedance specified for the ** package , the center thermal pad is soldered to the pcb ground plane. 19. higher temperatures is required based on the solder melting po int. typical temperatures for solder are 220 5oc with sn-pb or 245 5oc with sn-ag-cu paste. refer to the solder manufacturer specifications. [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 31 of 33 development tool selection software psoc designer at the core of the psoc development software suite is psoc designer. used by thousands of psoc developers, this robust software has been facilitating psoc designs for half a decade. psoc designer is available free of charge at http://www.cypress.com under design resources > software and drivers. psoc programmer flexible enough to be used on the bench in development, yet suitable for factory prog ramming, psoc programmer works either as a standalone programming application or it can operate directly from psoc designer or psoc express. psoc programmer software is compatible with both psoc ice-cube in-circuit emulator and psoc miniprog. psoc programmer is available free of charge at http://www.cypress.com/psocpro- grammer. hi-tech c lite compiler hi-tech c lite is an ansi c compiler optimized for psoc to deliver dense, efficient executable code for a smaller-than-ever footprint. hi-tech c lite is available for download at http://www.cypress.htsoft.com. to install the hi-tech lite version, download the complier ins tallation file from hi-tech and choose the lite option when prompted for a registration key. the lite version can be upgraded to the 45-day full featured evaluation version or the pro version at any time, however the pro version can only be enabled with a purchased registration key. hi-tech c pro compiler hi-tech c pro is an optional upgrade to psoc designer that offers all of the benefits of hi-tech c lite with additional features. hi-tech c pro is available for purchase either at the cypress online store or at http://www.cypress.htsoft.com. hi-tech c pro is recommended for touchscre en applications using the multi-touch all-point cy8ctma120 device. cy3202-c imagecraft c compiler cy3202 is the optional upgrade to psoc designer that enables the imagecraft c compiler. it can be purchased from the cypress online store. at http://www.cypress.com , click the online store shopping cart icon at the bottom of the web page, and click psoc (programmable system-on-chip) to view a current list of available items. evaluation tools all evaluation tools can be purchased from the cypress online store. cy3210-miniprog1 the cy3210-miniprog1 kit allows a user to program psoc devices through the miniprog1 programming unit. the miniprog is a small, compact prototyping pr ogrammer that connects to the pc through a provided usb 2.0 cable. the kit includes: miniprog programming unit minieval socket programming and evaluation board 28-pin cy8c29466-24pxi pdip psoc device sample 28-pin cy8c27443-24pxi pdip psoc device sample psoc designer software cd getting started guide usb 2.0 cable device programmers all device programmers can be purchased from the cypress online store. cy3216 modular programmer the cy3216 modular programmer kit features a modular programmer and the miniprog1 programming unit. the modular programmer includes three programming module cards and supports multiple cypress products. the kit includes: modular programmer base 3 programming module cards miniprog programming unit psoc designer software cd getting started guide usb 2.0 cable cy3207issp in-system serial programmer (issp) the cy3207issp is a production programmer. it includes protection circuitry and an industrial case that is more robust than the miniprog in a production-programming environment. note : cy3207issp needs special software and is not compatible with psoc programmer. the kit includes: cy3207 programmer unit psoc issp software cd 110 ~ 240v power supply, euro-plug adapter usb 2.0 cable [+] feedback
CY8CTMG120 document number: 001-46929 rev. *b page 32 of 33 accessories (emulation and programming) third party tools several tools have been specially designed by the following 3rd-party vendors to accompany psoc devices during devel- opment and production. specific details for each of these tools can be found at http://www.cypress.com under design resources > evaluation boards. build a psoc emulator into your board for details on how to emulate your circuit before going to volume production using an on-chip debug (ocd) non-production psoc device, see application note an2323 ?debugging - build a psoc emulator into your board?. ordering information. ordering code definitions package ordering code flash (bytes) sram (bytes) temperature range single-touch enabled multi-touch gesture enabled multi-touch all-point enabled x/y sensor inputs 56-pin (8x8 mm) qfn CY8CTMG120-56lfxi 16k 1k -40c to +85c y y n up to 44 56-pin (8x8 mm) qfn (tape and reel) CY8CTMG120-56lfxit 16k 1k -40c to +85c y y n up to 44 100-pin ocd tqfp CY8CTMG120-00axi 16k 1k -40c to +85c y y n up to 44 cy 8 c tmg xxx-56xx package type:thermal rating: px = pdip pb-freec = commercial sx = soic pb-freei = industrial pvx = ssop pb-freee = extended lfx/lkx = qfn pb-free ax = tqfp pb-free bvx = vfbga pb-free pin count: 56-pin part number family code: tmg = multi-touch touchscreen controller technology code: c = cmos marketing code: 8 = cypress psoc [+] feedback
document number: 001-46929 rev. *b revised july 29, 2008 page 33 of 33 truetouch?, psoc designer?, programmable system-on-chip?, and psoc express? are trademarks and psoc? is a registered trademark of cypress semiconductor corp. all other trademarks or registered trademarks referenced herein are property of the respective corporations. purchase of i2c components from cypress or one of its sublicensed associated companies conveys a license under the philips i2c patent rights to use these components in an i2c system, provided that the system conforms to the i2c stan dard specification as defined by philips. all products and company names mentioned in this document may be the trademarks of their respective holders. CY8CTMG120 ? cypress semiconductor corporation, 2008. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rig hts. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypres s. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a ma lfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions . cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cente rs, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb document title: CY8CTMG120 truetouch? multi-touch gesture touchscreen controller document number: 001-46929 revision ecn orig. of change submission date description of change ** 2518134 dso/aesa 06/18/08 new data sheet *a 2523303 dso/pyrs 06/30/08 updated x/y sensor inputs to 44 and supported screen sizes to 8.4? and below *b 2549257 yom/pyrs 08/06/08 added other sections based on psoc data sheets [+] feedback

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